1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor storage unit, and, more specifically, to a non-volatile semiconductor storage unit having a floating gate replacement, and method for making the same.
2. Description of the Prior Art
Computers conventionally use rotating magnetic media for data storage in form of magnetic hard disk drives (HDD). Though widely used and commonly accepted, such hard disk drives suffer from a variety of deficiencies. Access latency, higher power dissipation, increased physical size, and inability to withstand any physical shock justifies a new type of storage device. Other dominant semiconductor based storage devices are dynamic random access memory (DRAM) and static random access memory (SRAM). Both DRAM and SRAM are volatile and very costly but have faster random read/write time HDDs.
Non-volatile or solid-state-nonvolatile-memory (SSNVM) devices, such as NOR/NAND flash, provide higher access times and higher input/output performance (IOP) speed, lower power dissipation, smaller physical size and higher reliability, however usually at a cost which tends to be multiple times higher than HDDs. Although NAND Flash is more costly, it has replaced HDDs in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices.
Currently many devices use combinations of electronically-erasable programmable read only memory (EEPROM)/NOR, NAND, HDD, and DRAM. Including multiple memory technologies in a single product typically adds to the design complexity, time-to-market, and increases cost. For example, the handheld multimedia devices which incorporate NAND Flash, DRAM and EEPROM/NOR Flash are more complex devices to design, have higher costs to manufacture, and take longer to reach the market than devices incorporating fewer memory technologies. As a further disadvantage to such a device, incorporating multiple memories often increases the device's size, reducing its appeal to the consumer.
It is quite clear in the technical community that non-volatile memories are finding increasingly new applications, and this is expected to continue to explode due to the spectacular demands in portable devices. Mobile phones, MP3 players, and other consumer electronics are expected to use increasingly more NVRAM instead of commonly-used NOR-flash memory. Microcontrollers with internal flash, automobiles, and other information processing systems are also expected to replace flash with NVRAM. It is also believed that current volatile DRAM will be replaced by MRAM or spin-torque STTRAM, in the future.
As the process geometry is getting smaller, the design of NAND Flash and DRAM memory is becoming more difficult to scale. For example, NAND Flash has issues related to capacitive coupling, few electrons/bit, poor error-rate performance, and reduced reliability due to decreased read-write endurance. It is believed that NAND flash, especially multi-bit designs, would be extremely difficult to scale below 45 nano meters (nm). Likewise, DRAM has issues related to scaling of the trench capacitors, leading to very complex designs which are becoming very difficult to manufacture and leading to higher cost.
A known problem with manufacturing NAND flash is limitations in size or dimensions of its floating gate. FIG. 1 shows a prior art NAND flash cell. The N-diffusion wells may be formed on a P-substrate, as shown in the example of FIG. 1. Four floating gates are shown, each appearing between two N-diffusion wells and below a polysilicon word line (“Poly WL”). During operation, the floating gate serves to store electrons (charge) for changing the threshold voltage of the corresponding storage unit.
More specifically, in FIG. 1, a prior art memory array 100 made of a multiplicity of storage units (each storage unit being a flash memory), one of which is shown as storage unit 137, with a close-up view 120. Each storage unit 137 comprises two N-diffusion wells 133 formed in P-substrate 138, and a floating gate 135 formed below polysilicon word line 125 and the P-substrate 138, as better shown in cross-sectional view 140, cut along Y-Y of view 120. Cross-sectional view 170, cut along X-X of view 120, further shows that the floating gate 135 sharing the same word line 125 is electrically isolated by trenches 139 formed in P-substrate 138. Two floating gates are shown formed in view 140 on top of the P-Substrate 138 and below a respective word line 135. Each of these floating gates traditionally contain an intermediate oxide-nitride-oxide formed between a first and second layer of polysilicon. Silicon dioxide (SiO2), is primarily used for the oxide layers, and silicon nitride (SiN) for the nitride layer.
Prior art manufacturing processes employ a chemical vapor deposition (CVD) process to form the first polysilicon layer, followed by additional CVD processes to form the oxide, nitride and oxide layers. The SiO2 and SiN are deposited using different CVD tools, adding to the cost and time it takes to form the prior art flash memory of FIG. 1.
In the current process of making the NAND-flash shown in FIG. 1, thermally-oxidized silicon (Si) surface processing steps are performed, typically sequentially, leading to the formation of the two polysilicon layers, referred to as “Poly1” and “Poly2” with an inter-poly oxide-nitride-oxide (ONO) layer. The Poly1 layer is formed first, and is generally referred to as the floating gate. The Poly2 layer is generally referred to as the control gate. The ONO layer is formed between Poly1 and Poly2. The ONO layer includes a first oxide layer, formed on top of the Poly1 layer, a nitride layer formed on top of the first oxide layer, and a second oxide layer formed on top of the nitride layer. The Poly2 is formed on top of the second oxide layer. Thus, a chemical vapor deposition (CVD) process is used to make polysilicon, followed by additional CVD processes to make the first oxide, nitride, and second oxide layers comprising the ONO layer.
As scalability has been exploited, thereby increasing memory density, the floating gate has been reduced in size or dimensions. As the floating gate 135 becomes smaller, it becomes more difficult to balance charge retention with memory read/write speed. The shrinking dimensions of the floating gate 135 have or will soon reach their limitations, resulting in a density plateau for future flash memory products.
Accordingly, what is needed is a floating gate replacement for a nonvolatile semiconductor memory device where the floating gate replacement is capable of scaling beyond the limits of a traditional floating gate, thus increasing the density, capacity, and speed of the nonvolatile semiconductor memory device.